// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// -----------------------------------------------------------------------------
// Author 		: HiDark 1173296519@qq.com
// File   		: sram_ctr_ahb.v
// Create 		: 2023-12-24 16:21:23
// Description	: 
// Editor 		: tab size (4)
// -----------------------------------------------------------------------------

module sram_ctr_ahb
(
    // Inputs
    input           hclk,
    input           hresetn,
    input           hwrite,
    input   [1:0]   htrans,
    input   [2:0]   hsize,
    input   [31:0]  haddr,
    input   [2:0]   hburst,
    input   [31:0]  hwdata,
    input   [31:0]  sram_q,
    // Outputs    
    output          hready,
    output  [1:0]   hresp,
    output  [31:0]  hrdata,
    output          sram_csn,
    output          sram_wen,
    output  [11:0]  sram_a,
    output  [31:0]  sram_d
);
//-----HTRANS TYPE-----
parameter   IDLE    = 2'b00,
            BUSY    = 2'b01,
            NONSEQ  = 2'b10,
            SEQ     = 2'b11;
//---- HSIZE TYPE ----
parameter   BIT8    = 3'b000,
            BIT16   = 3'b001,
            BIT32   = 3'b010;//由于题目要求

//---- HBRUST TYPE ----   
parameter   SINGAL  = 3'b000, 
            INCR    = 3'b001,
            WRAP4   = 3'b010,
            INCR4   = 3'b011,
            WRAP8   = 3'b100,
            INCR8   = 3'b101,
            WRAP16  = 3'b110,
            INCR16  = 3'b111;

//----- HRESP TYPE -----    
parameter   OKAY    = 2'b00   ,
            ERROR   = 2'b01   ,
            SPLIT   = 2'b10   ,
            RETRY   = 2'b11   ; 

reg     [31:0]  haddr_r;    
reg             hwrite_r; 
reg     [1:0]   htrans_r;   
wire    [31:0]  sram_rd_addr,sram_wr_addr;

//-----------------------------------------------------------------
// Write enable and Write addr delay one beat
//-----------------------------------------------------------------
always @(posedge hclk or negedge hresetn) begin 
    if(!hresetn) begin
        haddr_r  <= 0;
        hwrite_r <= 0;
        htrans_r <= 0;
    end
    else begin
        haddr_r  <= haddr;
        hwrite_r <= hwrite;
        htrans_r <= htrans;
    end
end
assign sram_rd_addr = haddr;
assign sram_wr_addr = haddr_r;
//-----------------------------------------------------------------
// SRAM out port
//-----------------------------------------------------------------


assign sram_csn = ~((htrans == NONSEQ)|(htrans == SEQ));      
assign sram_wen = ~(hwrite_r&((htrans_r == NONSEQ)|(htrans_r == SEQ)));      
assign sram_a   = hwrite_r?sram_wr_addr[11:2]:sram_rd_addr[11:2];  
assign sram_d   = hwdata; 

//-----------------------------------------------------------------
// Only SRAM , always vaild 
//-----------------------------------------------------------------
assign hready   = 1'b1;
assign hresp    = OKAY;
assign hrdata   = sram_q;

endmodule